To save areas and costs, a high-end communication chip generally uses an eDRAM (embedded dynamic random access memory, embedded dynamic random access memory); and a pseudo two-port (PTP) eDRAM of IBM (International Business Machines Corporation, International Business Machines Corporation) is generally used as a memory storing a QIT (Queue Information Table, queue information table). However, when a bank (bank) conflict occurs on the PTP, performance is reduced. If no bank conflict occurs on the PTP, a write bandwidth of 600 Mpps and a read bandwidth of 600 Mpps can be reached, and the total bandwidth is 1200 Mpps. However, if a bank conflict occurs on the PTP, the total bandwidth in a worst circumstance may be 300 Mpps, which obviously affects the system performance seriously. In the prior art, the bank conflict is handled in the following manner:
A bank address is separated from an uncoded total address, and the bank address is sent to an embedded SRAM (Static RAM, static RAM); the SRAM stores a table in which uncoded addresses correspond to encoded addresses on a one-to-one basis, where the uncoded addresses and the encoded addresses exist in the form of specific addresses in the SRAM and are represented by binary numbers, that is, the uncoded address can indicate not only the bank address, but also the uncoded total address, and the encoded address can indicate not only the bank address, but also an encoded total address; a corresponding encoded bank address is obtained through query according to the uncoded bank address sent to the SRAM, and the encoded total address is obtained upon address aggregation. The uncoded total address includes the bank address.
However, in the prior art, when a bank conflict is handled, the bit width of the bank address is five bits at most, featuring a small bit width and obvious periodicity. As a result, the encoded total address regularly belongs to the same bank, which causes poor anti-attack and anti-interference capabilities. In addition, when a table in the SRAM is queried, a 2N*N (N indicates the number of bits) bit capacity of the SRAM needs to be occupied, thereby requiring a lot of resources and high costs.